1. Technical Field of the Invention
The present invention relates to memory cells protected against current or voltage spikes, in particular SRAM memory cells.
2. Description of Related Art
The continuing progressive miniaturization of electronic circuits allows smaller and smaller circuits having an increasingly higher performance to be obtained. On the other hand, these circuits are more and more sensitive to their external environment, and in particular to spurious logic events caused by an input of energy originating from outside of the circuit.
A spurious logic event is a localized change of state or a transitional state resulting in a voltage spike and/or a current spike at one point in an integrated circuit. By definition, a spurious event is unpredictable or practically so. Spurious logic events can have different origins.
A spurious logic event is, for example, induced by the impact of an energetic charged particle at one point of an integrated circuit. Such a spurious event is known as a ‘Single Event Upset’ or SEU. This type of spurious event appears in integrated circuits employed for applications in space, because of the radiation encountered outside of the protecting atmospheric and magnetospheric layers of the earth. This type of spurious event also occurs more and more frequently in integrated circuits for terrestrial applications, especially for the highest integration level technologies, such as 0.25 micron, 0.18 micron and 0.12 micron technologies and below.
A spurious logic event may also be induced by localized capacitive coupling between two layers of the same integrated circuit. This case is often referred to as a “glitch.”
Whatever its origin, a spurious event generally results in a voltage and/or a current spike on a digital or analog signal at an affected point in a circuit formed by the point of impact of the energetic particle, in the case of a spurious event of the SEU type.
If the equivalent capacitance of the circuit downstream of the affected point is denoted C, the voltage variation ΔV at the affected point being considered can be written ΔV=ΔQ/C, ΔQ being the charge variation resulting from the impact. The voltage variation ΔV is generally of very short duration, much shorter for example than the period of a clock signal controlling the circuit.
A spurious event may, or may not, have serious consequences for the downstream circuit that it affects.
For example, for a downstream circuit only using logic signals, if the voltage variation ΔV is small enough not to cause a change of state, the interference effect disappears in a reasonably short time, with no consequences for the downstream circuit. This is notably the case when the equivalent downstream capacitance is large or when the charge variation ΔQ is small.
On the contrary, if the voltage variation ΔV is larger, and notably if it is large enough to modify the value of a logic signal, then the consequences can be serious.
In particular, in the case of an SRAM memory cell, the voltage variation ΔV may reach a level such that the logic level stored in a data storage node is modified, together with the complementary logic level, so that the memory cell finds itself in a different stable state from its initial state prior to the arrival of the cause of interference.
Because of the increasing miniaturization of electronic circuits, and in particular of memory cells, the capacitance C of the junctions in which logic information is stored is decreasing, so that the voltage variations generated by the appearance of a spurious logic event often reach the threshold levels beyond which the stored information is modified, even for a small quantity of incident charge. Various methods are currently being used for protecting memory cells against spurious logic events.
In this regard, reference may be made to U.S. Pat. No. 5,570,313, the disclosure of which is hereby incorporated by reference, in which redundant data storage nodes are used for storing information in at least one pair of complementary nodes and in which, in order to restore information stored in one node of a pair to its initial state following a spurious event, the information stored in the other node is used.
This type of technique is effective for protecting a circuit against a localized spurious logic event, but it is ineffective for providing protection against spurious events affecting two complementary data storage nodes.
There is a need in the art to overcome this drawback and to provide a memory cell with improved protection against spurious events.